DESIGN OF A SINGLE-PHASE CASCADED H-BRIDGE MULTILEVEL INVERTER
Keywords:
inverter, h-bridge, cascaded, spwmAbstract
The significant disadvantages of two-level inverter include high harmonic distortion, limited
output voltage waveform due to only two voltage levels and higher switching losses. This paper
proposed a modelling approach for designing a single-phase cascaded H bridge multilevel
inverter with a resistive load. The fundamental contribution of this project is the simplification of
the suggested system: two equal DC sources, each equivalent to 1kVdc, a 50 Hz working
frequency, and eight MOSFET switches. The pulse is created using the SPWM bipolar multicarrier
approach, which compares the modulating signal with four phase-locked carrier signals. The
appropriate modulating index, which reflects the relationship between the fundamental voltage
and the input dc voltage, has been determined to generate an output voltage of 1kVrms. This can
be accomplished using MATLAB/Simulink to build and simulate a single-phase cascaded H bridge
multilevel inverter with a resistive load. Theoretical work has been done to verify the suggested
system's correctness. For a better understanding, these values will be compared to simulation
findings. The result shows that sinusoidal voltage values of 2000 Vpeak with a fundamental
voltage of 1410 V were obtained in the form of a five-level staircase with the following values:
2000V, 1000V, 0V, -1000V, -2000V. However, because of the high-frequency PWM inverter, an
LC filter was utilized to filter out the harmonics, resulting in sinusoidal output voltage and lower
total harmonics.
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